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MEX Observations Temporarily Suspended, Solid-state memory problems
post Nov 2 2011, 01:20 AM
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MEX Observations Temporarily Suspended

-- Hungry4info (Sirius_Alpha)
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post Feb 15 2012, 09:39 AM
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MEX back to full science operations now. After a lot of work.


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post Feb 17 2012, 03:55 AM
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QUOTE (cndwrld @ Feb 15 2012, 05:39 AM) *

This is a great writeup, btw. Came here to link to it!

I'm still curious what causes the SSMM errors, though. A comment here:
... suggests that the memory system is having bit errors.

Though in the way ESA describes it-- "errors during the transfer of data from the MTL(in the SSMM) to the command cache"-- I wonder if the errors occur not in the memory, but somewhere in a bus between the SSMM and the command cache in the CPU. They also suggest the redundant memory controller didn't do any better.

Page 127 here has a memory system diagram for VEX, pretty much like MEX:

That doesn't really help show which bus could be the culprit, though, because they're basically all redundant. I suppose it could be multi-bit-errors in the flash percolating all the way through either memory controller. Except the system should catch those. So I can talk in circles and not know what's really going wrong here. And I'm curious. Anyone know of any other sources?
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